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CY8CLED16
EZ-ColorTM HB LED Controller
Features
HB LED Controller Configurable Dimmers Support up to 16 Independent LED Channels 8-32 Bits of Resolution per Channel Dynamic Reconfiguration Enables LED Controller plus other Features; Battery Charging, Motor Control... Visual Embedded Design, PSoC Express LED Based Express Drivers * Binning Compensation * Temperature Feedback * DMX512 PrISM Modulation Technology Reduces Radiated EMI Reduces Low Frequency Blinking Powerful Harvard Architecture Processor M8C Processor Speeds to 24 MHz 3.0 to 5.25V Operating Voltage Operating Voltages down to 1.0V using On-Chip Switch Mode Pump (SMP) Industrial Temperature Range: -40C to +85C Programmable Pin Configurations 25 mA Sink on all GPIO Pull up, Pull down, High Z, Strong, or Open Drain Drive Modes on all GPIO Up to eight Analog Inputs on GPIO Configurable Interrupt on all GPIO
Advanced Peripherals (PSoC Blocks) 16 Digital PSoC Blocks Provide: * 8 to 32-Bit Timers, Counters, and PWMs * Up to 2 Full-Duplex UART * Multiple SPITM Masters or Slaves * Connectable to all GPIO Pins 12 Rail-to-Rail Analog PSoC Blocks Provide: * Up to 14-Bit ADCs * Up to 9-Bit DACs * Programmable Gain Amplifiers * Programmable Filters and Comparators Complex Peripherals by Combining Blocks Flexible On-Chip Memory 32K Flash Program Storage 50,000 Erase/Write Cycles 2K SRAM Data Storage In-System Serial Programming (ISSP) Partial Flash Updates Flexible Protection Modes EEPROM Emulation in Flash Complete Development Tools Free Development Software * PSoC DesignerTM * PSoC ExpressTM Full-Featured, In-Circuit Emulator and Programmer Full Speed Emulation Complex Breakpoint Structure 128 KBytes Trace Memory

EZ-Color HB LED Controller Preliminary Data Sheet
Cypress Semiconductor Corporation Document Number: 001-13105 Rev. **
*198 Champion Court*San Jose, CA 95134-1709*408-943-2600 Revised June 12, 2007
CY8CLED16
Overview
Block Diagram
Port 7 Port 6 Port 5 Port 4 Port 3 Port 2 Port 1 Port 0 Analog Drivers
SYSTEM BUS
Global Digital Interconnect SRAM 2K Interrupt Controller
Global Analog Interconnect Flash 32K
SROM
PSoC CORE
Sleep and Watchdog
CPU Core (M8C)
Multiple Clock Sources (Includes IMO, ILO, PLL, and ECO)
DIGITAL SYSTEM
Digital Block Array
ANALOG SYSTEM
Analog Ref.
Analog Block Array
Analog Input Muxing
Digital Clocks
Two Multiply Accums.
POR and LVD Decimator I 2C System Resets
Internal Voltage Ref.
Switch Mode Pump
SYSTEM RESOURCES
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EZ-Color Functional Overview
Cypress' EZ-Color family of devices offers the ideal control solution for High Brightness LED applications requiring intelligent dimming control. EZ-Color devices combine the power and flexibility of PSoC (Programmable System-on-ChipTM); with Cypress' PrISM (precise illumination signal modulation) modulation technology providing lighting designers a fully customizable and integrated lighting solution platform. The EZ-Color family supports up to 16 independent LED channels with up to 32 bits of resolution per channel, enabling lighting designers the flexibility to choose the LED array size and color quality. PSoC Express software, with lighting specific drivers, can significantly cut development time and simplify implementation of fixed color points through temperature and LED binning compensation. EZ-Color's virtually limitless analog and digital customization allow for simple integration of features in addition to intelligent lighting, such as Battery Charging, Image Stabilization, and Motor Control during the development process. These features, along with Cypress' best-in-class quality and design support, make EZ-Color the ideal choice for intelligent HB LED control applications.
to 2.5% over temperature and voltage. The 24 MHz IMO can also be doubled to 48 MHz for use by the digital system. A low power 32 kHz ILO (internal low speed oscillator) is provided for the Sleep timer and WDT. If crystal accuracy is desired, the ECO (32.768 kHz external crystal oscillator) is available for use as a Real Time Clock (RTC) and can optionally generate a crystal-accurate 24 MHz system clock using a PLL. The clocks, together with programmable clock dividers (as a System Resource), provide the flexibility to integrate almost any timing requirement into the EZ-Color device. EZ-Color GPIOs provide connection to the CPU, digital and analog resources of the device. Each pin's drive mode may be selected from eight options, allowing great flexibility in external interfacing. Every pin also has the capability to generate a system interrupt on high level, low level, and change from last read.
The Digital System
The Digital System is composed of 16 digital PSoC blocks. Each block is an 8-bit resource that can be used alone or combined with other blocks to form 8, 16, 24, and 32-bit peripherals, which are called user module references. Digital peripheral configurations include those listed below.

Target Applications

LCD Backlight Large Signs General Lighting Architectural Lighting Camera/Cell Phone Flash Flashlights
PrISM (8 to 32 bit) PWMs (8 to 32 bit) PWMs with Dead band (8 to 32 bit) Counters (8 to 32 bit) Timers (8 to 32 bit) UART 8 bit with selectable parity (up to 4) SPI master and slave (up to 4 each) I2C slave and multi-master (1 available as a System Resource) Cyclical Redundancy Checker/Generator (8 to 32 bit) IrDA (up to 4) Generators (8 to 32 bit)
The PSoC Core
The PSoC Core is a powerful engine that supports a rich feature set. The core includes a CPU, memory, clocks, and configurable GPIO (General Purpose IO). The M8C CPU core is a powerful processor with speeds up to 48 MHz, providing a four MIPS 8-bit Harvard architecture microprocessor. The CPU utilizes an interrupt controller with 25 vectors, to simplify programming of real time embedded events. Program execution is timed and protected using the included Sleep and Watch Dog Timers (WDT). Memory encompasses 32 KB of Flash for program storage, 2 KB of SRAM for data storage, and up to 2 KB of EEPROM emulated using the Flash. Program Flash utilizes four protection levels on blocks of 64 bytes, allowing customized software IP protection. The EZ-Color family incorporates flexible internal clock generators, including a 24 MHz IMO (internal main oscillator) accurate
The digital blocks can be connected to any GPIO through a series of global buses that can route any signal to any pin. The buses also allow for signal multiplexing and for performing logic operations. This configurability frees your designs from the constraints of a fixed peripheral controller. Digital blocks are provided in rows of four, where the number of blocks varies by EZ-Color device family. This allows you the optimum choice of system resources for your application. Family resources are shown in the table titled EZ-Color Device Characteristics on page 4.
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CY8CLED16
Figure 1. Digital System Block Diagram
Port 7 Port 6 Port 5 Port 4 Port 3 Port 2 Port 1 Port 0
The Analog System
The Analog System is composed of 12 configurable blocks, each comprised of an opamp circuit allowing the creation of complex analog signal flows. Analog peripherals are very flexible and can be customized to support specific application requirements. Some of the more common EZ-Color analog functions (most available as user modules) are listed below.

Digital Clocks From Core
To System Bus
To Analog System
DIGITAL SYSTEM
Digital PSoC Block Array
Row Input Configuration
Analog-to-digital converters (up to 4, with 6- to 14-bit resolution, selectable as Incremental, Delta Sigma, and SAR) Filters (2, 4, 6, or 8 pole band-pass, low-pass, and notch) Amplifiers (up to 4, with selectable gain to 48x) Instrumentation amplifiers (up to 2, with selectable gain to 93x) Comparators (up to 4, with 16 selectable thresholds) DACs (up to 4, with 6- to 9-bit resolution) Multiplying DACs (up to 4, with 6- to 9-bit resolution) High current output drivers (four with 40 mA drive as a Core Resource) 1.3V reference (as a System Resource) DTMF Dialer Modulators Correlators Peak Detectors Many other topologies possible
Row 0
DBB00 DBB01 DCB02
4 DCB03 4
Row Output Configuration

8
8 8 Row Input Configuration
8
Row 1
DBB10 DBB11 DCB12
4 DCB13 4

Row Output Configuration
Row Input Configuration
Row 2
DBB20 DBB21 DCB22
4 DCB23 4
Row Output Configuration
Row Input Configuration
Row 3
DBB30 DBB31 DCB32
4 DCB33 4

Row Output Configuration
GIE[7:0] GIO[7:0]
Global Digital Interconnect
GOE[7:0] GOO[7:0]
Analog blocks are provided in columns of three, which includes one CT (Continuous Time) and two SC (Switched Capacitor) blocks, as shown in the figure below.
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Figure 2. Analog System Block Diagram
P0[7] P0[5] P0[3] P0[1] AGNDIn RefIn P0[6] P0[4] P0[2] P0[0] P2[6]
Additional System Resources
System Resources, some of which have been previously listed, provide additional capability useful to complete systems. Resources include a multiplier, decimator, switch mode pump, low voltage detection, and power on reset. Statements describing the merits of each system resource are presented below.
P2[3]
Digital clock dividers provide three customizable clock frequencies for use in applications. The clocks can be routed to both the digital and analog systems. Additional clocks can be generated using digital PSoC blocks as clock dividers. Multiply accumulate (MAC) provides fast 8-bit multiplier with 32-bit accumulate, to assist in general math and digital filters. The decimator provides a custom hardware filter for digital signal, processing applications including the creation of Delta Sigma ADCs. The I2C module provides 100 and 400 kHz communication over two wires. Slave, master, and multi-master modes are all supported. Low Voltage Detection (LVD) interrupts can signal the application of falling voltage levels, while the advanced POR (Power On Reset) circuit eliminates the need for a system supervisor. An internal 1.3 voltage reference provides an absolute reference for the analog system, including ADCs and DACs. An integrated switch mode pump (SMP) generates normal operating voltages from a single 1.2V battery cell, providing a low cost boost converter.
P2[4] P2[2] P2[0]

P2[1]
Array Input Configuration
ACI0[1:0]
ACI1[1:0]
ACI2[1:0]
ACI3[1:0]

Block Array
ACB00 ASC10 ASD20 ACB01 ASD11 ASC21 ACB02 ASC12 ASD22 ACB03 ASD13 ASC23
Analog Reference
Interface to Digital System RefHi RefLo AGND Reference Generators AGNDIn RefIn Bandgap
M8C Interface (Address Bus, Data Bus, Etc.)
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EZ-Color Device Characteristics
Depending on your EZ-Color device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 4 analog blocks. The following table lists the resources available for specific EZ-Color device groups. The device covered by this data sheet is shown in the highlighted row of the table. Table 1. EZ-Color Device Characteristics
PSoC Part Number CY8CLED04 CY8CLED08 CY8CLED16 CapSense Yes No No LED Channels Analog Columns Analog Outputs Analog Inputs Analog Blocks Digital Blocks Digital IO Digital Rows SRAM Size Flash Size 16K 16K 32K
4 8 16
56 44 64
1 2 4
4 8 16
48 12 12
2 4 4
2 4 4
6 12 12
1K 256 Bytes 2K
Getting Started
The quickest path to understanding the EZ-Color silicon is by reading this data sheet and using PSoC Express to create HB LED applications. This data sheet is an overview of the EZ-Color integrated circuit and presents specific pin, register, and electrical specifications. For up-to-date Ordering, Packaging, and Electrical Specification information, reference the latest device data sheets on the web at http://www.cypress.com/ez-color.
Consultants
Certified PSoC Consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC Consultant, go to the following Cypress support web site: http://www.cypress.com/support/cypros.cfm.
Technical Support
PSoC application engineers take pride in fast and accurate response. They can be reached with a 4-hour guaranteed response at http://www.cypress.com/support/login.cfm.
Development Kits
Development Kits are available from the following distributors: Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store at http://www.onfulfillment.com/cypressstore/ contains development kits, C compilers, and all accessories for PSoC development. Click on EZ-Color to view a current list of available items.
Application Notes
A long list of application notes will assist you in every aspect of your design effort. To view the PSoC application notes, go to the http://www.cypress.com web site and select Application Notes under the Design Resources list located in the center of the web page. Application notes are listed by date by default.
Technical Training Modules
Free PSoC technical training modules are available for users new to PSoC. Training modules cover designing, debugging, advanced analog, CapSense, and HB LED. Go to http://www.cypress.com/techtrain.
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CY8CLED16
Development Tools
PSoC Express is a high-level design tool for creating embedded systems with devices using Cypress's PSoC Mixed-Signal technology. With PSoC Express you create a complete embedded solution including all necessary on-chip peripherals, block configuration, interrupt handling and application software without writing a single line of assembly or C code. PSoC Express solves design problems the way you think about the system:

Most of the files associated with a project are automatically generated by PSoC Express during the build process, but you can make changes directly to the custom.c and custom.h files and also add your own custom code to the project in the Project Manager.
Application Editor
The Application Editor allows you to edit custom.c and custom.h as well as any C or assembly language source code that you add to your project. With PSoC Express you can create application software without writing a single line of assembly or C code, but you have a full featured application editor at your finger tips if you want it. Build Manager The Build Manager gives you the ability to build the application software, assign pins, and generate the data sheet, schematic, and BOM for your project. Board Monitor The Board Monitor is a debugging tool designed to be used while attached to a prototype board through a communication interface that allows you to monitor changes in the various design elements in real time. The default communication for the board monitor is I2C. It uses the CY3240-I2USB I2C to USB Bridge Debugging/Communication Kit. Tuners A Tuner is a visual interface for the Board Monitor that allows you to view the performance of the HB LED drivers on your test board while your program is running, and manually override values and see the results.
Select input and output devices based upon system requirements. Add a communications interface and define its interface to system (using registers). Define when and how an output device changes state based upon any and all other system devices. Based upon the design, automatically select one or more PSoC Mixed-Signal Controllers that match system requirements. Figure 3. PSoC Express
Hardware Tools PSoC Express Subsystems
Express Editor The Express Editor allows you to create designs visually by dragging and dropping inputs, outputs, communication interfaces, and other design elements, and then describing the logic that controls them. Project Manager The Project Manager allows you to work with your applications and projects in PSoC Express. A PSoC Express application is a top level container for projects and their associated files. Each project contains a design that uses a single PSoC device. An application can contain multiple projects so if you are creating an application that uses multiple PSoC devices you can keep all of the projects together in a single application. In-Circuit Emulator A low cost, high functionality ICE (In-Circuit Emulator) is available for development support. This hardware has the capability to program single devices. The emulator consists of a base unit that connects to the PC by way of the USB port. The base unit is universal and will operate with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full speed (24 MHz) operation. I2C to USB Bridge The I2C to USB Bridge is a quick and easy link from any design or application's I2C bus to a PC via USB for design testing, debugging and communication.
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Document Conventions
Acronyms Used
The following table lists the acronyms that are used in this document.
Acronym AC ADC API CPU CT DAC DC ECO EEPROM FSR GPIO GUI HBM ICE ILO IMO IO IPOR LSb LVD MSb PC PLL POR PPOR PSoCTM PWM SC SLIMO SMP SRAM alternating current analog-to-digital converter application programming interface central processing unit continuous time digital-to-analog converter direct current external crystal oscillator electrically erasable programmable read-only memory full scale range general purpose IO graphical user interface human body model in-circuit emulator internal low speed oscillator internal main oscillator input/output imprecise power on reset least-significant bit low voltage detect most-significant bit program counter phase-locked loop power on reset precision power on reset Programmable System-on-ChipTM pulse width modulator switched capacitor slow IMO switch mode pump static random access memory Description
Units of Measure
A units of measure table is located in the Electrical Specifications section. Table 7 on page 15 lists all the abbreviations used to measure the PSoC devices.
Numeric Naming
Hexidecimal numbers are represented with all letters in uppercase with an appended lowercase `h' (for example, `14h' or `3Ah'). Hexidecimal numbers may also be represented by a `0x' prefix, the C coding convention. Binary numbers have an appended lowercase `b' (e.g., 01010100b' or `01000011b'). Numbers not indicated by an `h', `b', or 0x are decimal.
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CY8CLED16
Pin Information
Pinouts
The CY8CLED16 device is available in three packages which are listed and illustrated in the following tables. Every port pin (labeled with a "P") is capable of Digital IO. However, Vss, Vdd, SMP, and XRES are not capable of Digital IO. 28-Pin Part Pinout Table 2. 28-Pin Part Pinout (SSOP)
Pin No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Type Digital IO IO IO IO IO IO IO IO Power IO IO IO IO Power IO IO IO IO Input IO IO IO IO IO IO IO IO Power I I Analog I IO IO I
Pin Name
P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] SMP P1[7] P1[5] P1[3] P1[1] Vss P1[0] P1[2] P1[4] P1[6] XRES P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] Vdd
Description
Analog column mux input. Analog column mux input and column output. Analog column mux input and column output. Analog column mux input.
A, I, P0[7] A, IO, P0[5] A, IO, P0[3] A, I, P0[1] P2[7] P2[5] A, I, A, I, P2[3] P2[1] SMP I2C SCL, P1[7] I2C SDA, P1[5] P1[3] I2C SCL, XTALin, P1[1] Vss
28-Pin Device
1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15
Vdd P0[6], A, I P0[4], A, IO P0[2], A, IO P0[0], A, I P2[6], External VREF P2[4], External AGND P2[2], A, I P2[0], A, I XRES P1[6] P1[4], EXTCLK P1[2] P1[0], XTALout, I2C SDA
I I
Direct switched capacitor block input. Direct switched capacitor block input. Switch Mode Pump (SMP) connection to external components required. I2C Serial Clock (SCL). I2C Serial Data (SDA). Crystal (XTALin), I2C Serial Clock (SCL), ISSP-SCLK*. Ground connection. Crystal (XTALout), I2C Serial Data (SDA), ISSP-SDATA*. Optional External Clock Input (EXTCLK). Active high external reset with internal pull down. Direct switched capacitor block input. Direct switched capacitor block input. External Analog Ground (AGND). External Voltage Reference (VREF). Analog column mux input. Analog column mux input and column output. Analog column mux input and column output. Analog column mux input. Supply voltage.
SSOP
I IO IO I
LEGEND: A = Analog, I = Input, and O = Output. * These are the ISSP pins, which are not High Z at POR (Power On Reset).
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48-Pin Part Pinouts Table 3. 48-Pin Part Pinout (SSOP)
Pin No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Type Digital IO IO IO IO IO IO IO IO IO IO IO IO Power IO IO IO IO IO IO IO IO IO IO Power IO IO IO IO IO IO IO IO IO IO Input IO IO IO IO IO IO IO IO IO IO IO IO Power Analog I IO IO I
Pin Name
P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] SMP P3[7] P3[5] P3[3] P3[1] P5[3] P5[1] P1[7] P1[5] P1[3] P1[1] Vss P1[0] P1[2] P1[4] P1[6] P5[0] P5[2] P3[0] P3[2] P3[4] P3[6] XRES P4[0] P4[2] P4[4] P4[6] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] Vdd
Description
Analog column mux input. Analog column mux input and column output. Analog column mux input and column output. Analog column mux input.
A, I, P0[7] A, IO, P0[5] A, IO, P0[3] A, I, P0[1] P2[7] P2[5] A, I, P2[3] A, I, P2[1] P4[7] P4[5] P4[3] P4[1] SMP P3[7] P3[5] P3[3] P3[1] P5[3] P5[1] I2C SCL, P1[7] I2C SDA, P1[5] P1[3] I2C SCL, XTALin, P1[1] Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48-Pin Device
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
Vdd P0[6], A, I P0[4], A, IO P0[2], A, IO P0[0], A, I P2[6], External VREF P2[4], External AGND P2[2], A, I P2[0], A, I P4[6] P4[4] P4[2] P4[0] XRES P3[6] P3[4] P3[2] P3[0] P5[2] P5[0] P1[6] P1[4], EXTCLK P1[2] P1[0], XTALout, I2C SDA
I I
Direct switched capacitor block input. Direct switched capacitor block input.
SSOP
Switch Mode Pump (SMP) connection to external components required.
I2C Serial Clock (SCL). I2C Serial Data (SDA). Crystal (XTALin), I2C Serial Clock (SCL), ISSP-SCLK*. Ground connection. Crystal (XTALout), I2C Serial Data (SDA), ISSP-SDATA*. Optional External Clock Input (EXTCLK).
Active high external reset with internal pull down.
I I
I IO IO I
Direct switched capacitor block input. Direct switched capacitor block input. External Analog Ground (AGND). External Voltage Reference (VREF). Analog column mux input. Analog column mux input and column output. Analog column mux input and column output. Analog column mux input. Supply voltage.
LEGEND: A = Analog, I = Input, and O = Output. * These are the ISSP pins, which are not High Z at POR (Power On Reset).
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Table 4. 48-Pin Part Pinout (QFN**)
Pin No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Power I IO IO I IO IO I I I IO IO IO IO IO IO IO IO IO IO Input IO IO IO IO IO IO IO IO IO IO Power Type Digital IO IO IO IO IO IO Power Analog I I
Pin Name
P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] SMP P3[7] P3[5] P3[3] P3[1] P5[3] P5[1] P1[7] P1[5] P1[3] P1[1] Vss P1[0] P1[2] P1[4] P1[6] P5[0] P5[2] P3[0] P3[2] P3[4] P3[6] XRES P4[0] P4[2] P4[4] P4[6] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] Vdd P0[7] P0[5] P0[3]
Description
Direct switched capacitor block input. Direct switched capacitor block input.
48-Pin PSoC Device
P0[0], A, I P2[6], External VREF 38 37 36 35 34 33 32 31 30 29 28 27 26 25 P2[4], External AGND P2[2], A, I P2[0], A, I P4[6] P4[4] P4[2] P4[0] XRES P3[6] P3[4] P3[2] P3[0] P5[0] P5[2]
P0[3], A, IO P0[5], A, IO P0[7], A, I
48 47 46 45 44 43 13 14 15 16 P5[1] I2C SCL, P1[7] I2C SDA, P1[5] P1[3]
Switch Mode Pump (SMP) connection to external components required.
Crystal (XTALin), I2C Serial Clock (SCL), ISSP-SCLK*. Ground connection. Crystal (XTALout), I2C Serial Data (SDA), ISSP-SDATA*. Optional External Clock Input (EXTCLK).
Active high external reset with internal pull down.
Direct switched capacitor block input. Direct switched capacitor block input. External Analog Ground (AGND). External Voltage Reference (VREF). Analog column mux input. Analog column mux input and column output. Analog column mux input and column output. Analog column mux input. Supply voltage. Analog column mux input. Analog column mux input and column output. Analog column mux input and column output.
Document Number: 001-13105 Rev. **
I2C SCL, XTALin, P1[1] Vss I2C SDA, XTALout, P1[0] P1[2] EXTCLK, P1[4] P1[6]
I2C Serial Data (SDA).
17 18 19 20 21 22 23 24
I2C Serial Clock (SCL).
A, I, P2[3] A, I, P2[1] P4[7] P4[5] P4[3] P4[1] SMP P3[7] P3[5] P3[3] P3[1] P5[3]
1 2 3 4 5 6
MLF
(Top View)
7 8 9 10 11 12
42 41 40 39
Vdd P0[6], A, I P0[4], A, IO P0[2], A, IO
P2[5] P2[7] P0[1], A, I
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Table 4. 48-Pin Part Pinout (QFN**)
46 47 48 IO IO IO I P0[1] P2[7] P2[5] Analog column mux input.
LEGEND: A = Analog, I = Input, and O = Output. * These are the ISSP pins, which are not High Z at POR (Power On Reset). ** The QFN package has a center pad that must be connected to ground (Vss).
Register Reference
Register Conventions
Abbreviations Used The register conventions specific to this section are listed in the following table.
Convention R W L C # Description Read register or bit(s) Write register or bit(s) Logical register or bit(s) Clearable register or bit(s) Access is bit specific
Register Mapping Tables
This chapter lists the registers of the CY8CLED16 EZ-Color device. The device has a total register address space of 512 bytes. The register space is referred to as IO space and is divided into two banks. The XOI bit in the Flag register (CPU_F) determines which bank the user is currently in. When the XOI bit is set the user is in Bank 1. Note In the following register mapping tables, blank fields are reserved and should not be accessed.
Table 5. Register Map Bank 0 Table: User Space
Name PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 PRT3DR PRT3IE PRT3GS PRT3DM2 PRT4DR PRT4IE PRT4GS PRT4DM2 PRT5DR PRT5IE PRT5GS Addr (0,Hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name DBB20DR0 DBB20DR1 DBB20DR2 DBB20CR0 DBB21DR0 DBB21DR1 DBB21DR2 DBB21CR0 DCB22DR0 DCB22DR1 DCB22DR2 DCB22CR0 DCB23DR0 DCB23DR1 DCB23DR2 DCB23CR0 DBB30DR0 DBB30DR1 DBB30DR2 DBB30CR0 DBB31DR0 DBB31DR1 DBB31DR2 Addr (0,Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D Access # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # # W Name ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 ASC12CR0 ASC12CR1 ASC12CR2 ASC12CR3 ASD13CR0 ASD13CR1 ASD13CR2 ASD13CR3 ASD20CR0 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 Addr (0,Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 Acces RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name RDI2RI RDI2SYN RDI2IS RDI2LT0 RDI2LT1 RDI2RO0 RDI2RO1 RDI3RI RDI3SYN RDI3IS RDI3LT0 RDI3LT1 RDI3RO0 RDI3RO1 CUR_PP STK_PP IDX_PP MVR_PP MVW_PP I2C_CFG I2C_SCR I2C_DR I2C_MSCR INT_CLR0 INT_CLR1 INT_CLR2 INT_CLR3 Addr (0,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD Acces RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW # RW # RW RW RW RW
PRT5DM2 17 RW DBB31CR0 PRT6DR 18 RW DCB32DR0 PRT6IE 19 RW DCB32DR1 PRT6GS 1A RW DCB32DR2 PRT6DM2 1B RW DCB32CR0 PRT7DR 1C RW DCB33DR0 PRT7IE 1D RW DCB33DR1 Blank fields are Reserved and should not be accessed.
ASC21CR3 97 ASD22CR0 98 ASD22CR1 99 ASD22CR2 9A ASD22CR3 9B ASC23CR0 9C ASC23CR1 9D # Access is bit specific.
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CY8CLED16
Table 5. Register Map Bank 0 Table: User Space (continued)
Name Addr (0,Hex) Access Name PRT7GS 1E RW DCB33DR2 PRT7DM2 1F RW DCB33CR0 DBB00DR0 20 # AMX_IN DBB00DR1 21 W DBB00DR2 22 RW DBB00CR0 23 # ARF_CR DBB01DR0 24 # CMP_CR0 DBB01DR1 25 W ASY_CR DBB01DR2 26 RW CMP_CR1 DBB01CR0 27 # DCB02DR0 28 # DCB02DR1 29 W DCB02DR2 2A RW DCB02CR0 2B # DCB03DR0 2C # TMP_DR0 DCB03DR1 2D W TMP_DR1 DCB03DR2 2E RW TMP_DR2 DCB03CR0 2F # TMP_DR3 DBB10DR0 30 # ACB00CR3 DBB10DR1 31 W ACB00CR0 DBB10DR2 32 RW ACB00CR1 DBB10CR0 33 # ACB00CR2 DBB11DR0 34 # ACB01CR3 DBB11DR1 35 W ACB01CR0 DBB11DR2 36 RW ACB01CR1 DBB11CR0 37 # ACB01CR2 DCB12DR0 38 # ACB02CR3 DCB12DR1 39 W ACB02CR0 DCB12DR2 3A RW ACB02CR1 DCB12CR0 3B # ACB02CR2 DCB13DR0 3C # ACB03CR3 DCB13DR1 3D W ACB03CR0 DCB13DR2 3E RW ACB03CR1 DCB13CR0 3F # ACB03CR2 Blank fields are Reserved and should not be accessed. Addr (0,Hex) 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F Access RW # RW Addr (0,Hex) 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 MUL1_X A8 MUL1_Y A9 MUL1_DH AA MUL1_DL AB ACC1_DR1 AC ACC1_DR0 AD ACC1_DR3 AE ACC1_DR2 AF RDI0RI B0 RDI0SYN B1 RDI0IS B2 RDI0LT0 B3 RDI0LT1 B4 RDI0RO0 B5 RDI0RO1 B6 B7 RDI1RI B8 RDI1SYN B9 RDI1IS BA RDI1LT0 BB RDI1LT1 BC RDI1RO0 BD RDI1RO1 BE BF # Access is bit specific. Name ASC23CR2 ASC23CR3 Acces Name RW INT_MSK3 RW INT_MSK2 INT_MSK0 INT_MSK1 INT_VC RES_WDT DEC_DH DEC_DL DEC_CR0 DEC_CR1 W MUL0_X W MUL0_Y R MUL0_DH R MUL0_DL RW ACC0_DR1 RW ACC0_DR0 RW ACC0_DR3 RW ACC0_DR2 RW RW RW RW RW RW RW CPU_F RW RW RW RW RW RW RW CPU_SCR1 CPU_SCR0 Addr (0,Hex) DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF Acces RW RW RW RW RC W RC RC RW RW W W R R RW RW RW RW
RW # # RW
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
RL
# #
Table 6. Register Map Bank 1 Table: Configuration Space
Name PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1 PRT4DM0 PRT4DM1 PRT4IC0 PRT4IC1 PRT5DM0 PRT5DM1 PRT5IC0 PRT5IC1 Addr(1,Hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW DBB31FN DBB31IN DBB31OU DBB30FN DBB30IN DBB30OU DCB23FN DCB23IN DCB23OU DCB22FN DCB22IN DCB22OU DBB21FN DBB21IN DBB21OU Name DBB20FN DBB20IN DBB20OU Addr(1,Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Access RW RW RW Name ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 ASC12CR0 ASC12CR1 ASC12CR2 ASC12CR3 ASD13CR0 ASD13CR1 ASD13CR2 ASD13CR3 ASD20CR0 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3 Addr(1,Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 Acces s RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU RDI3RI RDI3SYN RDI3IS RDI3LT0 RDI3LT1 RDI3RO0 RDI3RO1 Name RDI2RI RDI2SYN RDI2IS RDI2LT0 RDI2LT1 RDI2RO0 RDI2RO1 Addr(1,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 RW RW RW RW RW RW RW RW RW RW RW Acces s RW RW RW RW RW RW RW
Blank fields are Reserved and should not be accessed.
# Access is bit specific.
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Table 6. Register Map Bank 1 Table: Configuration Space (continued)
Name PRT6DM0 PRT6DM1 PRT6IC0 PRT6IC1 PRT7DM0 PRT7DM1 PRT7IC0 PRT7IC1 DBB00FN DBB00IN DBB00OU DBB01FN DBB01IN DBB01OU DCB02FN DCB02IN DCB02OU DCB03FN DCB03IN DCB03OU DBB10FN DBB10IN DBB10OU DBB11FN DBB11IN DBB11OU DCB12FN DCB12IN DCB12OU DCB13FN DCB13IN DCB13OU Addr(1,Hex) 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 ACB00CR3 ACB00CR0 ACB00CR1 ACB00CR2 ACB01CR3 ACB01CR0 ACB01CR1 ACB01CR2 ACB02CR3 ACB02CR0 ACB02CR1 ACB02CR2 ACB03CR3 ACB03CR0 ACB03CR1 ACB03CR2 RW RW RW RW RW RW AMD_CR1 ALT_CR0 ALT_CR1 CLK_CR2 Access RW RW RW RW RW RW RW RW RW RW RW CLK_CR0 CLK_CR1 ABF_CR0 AMD_CR0 DCB33FN DCB33IN DCB33OU Name DCB32FN DCB32IN DCB32OU Addr(1,Hex) 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1 RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RW RW RW RW RW RW RW RW RW RW RW Access RW RW RW Name ASD22CR0 ASD22CR1 ASD22CR2 ASD22CR3 ASC23CR0 ASC23CR1 ASC23CR2 ASC23CR3 Addr(1,Hex) 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF # Access is bit specific. RW RW RW RW RW RW RW CPU_SCR1 CPU_SCR0 FLS_PR1 RW RW RW RW RW RW RW CPU_F DEC_CR2 IMO_TR ILO_TR BDG_TR ECO_TR Acces s RW RW RW RW RW RW RW RW OSC_GO_EN OSC_CR4 OSC_CR3 OSC_CR0 OSC_CR1 OSC_CR2 VLT_CR VLT_CMP Name Addr(1,Hex) D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF # # RW RL RW W W RW W RW RW RW RW RW RW RW R Acces s
Blank fields are Reserved and should not be accessed.
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CY8CLED16
Electrical Specifications
This chapter presents the DC and AC electrical specifications of the CY8CLED16 EZ-Color device. For the most up to date electrical specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com/ez-color. Specifications are valid for -40oC TA 85oC and TJ 100oC, except where noted. Refer to Table 23 for the electrical specifications on the internal main oscillator (IMO) using SLIMO mode. Figure 4. Voltage versus CPU Frequency, and IMO Frequency Trim Options
SLIMO Mode=1
4.75 Vdd Voltage 3.00 93 kHz CPU Frequency 4.75 Vdd Voltage
SLIMO Mode = 0
5.25
5.25
SLIMO Mode=0
The following table lists the units of measure that are used in this chapter. Table 7. Units of Measure
Symbol
oC
Unit of Measure degree Celsius decibels femto farad hertz 1024 bytes 1024 bits kilohertz kilohm megahertz megaohm microampere microfarad microhenry microsecond microvolts microvolts root-mean-square
lid ng Va rati n e io Op Reg
12 MHz 24 MHz
3.60
SLIMO Mode=1
SLIMO Mode=0
3.00
93 kHz
6 MHz IMO Frequency
12 MHz
24 MHz
Symbol W mA ms mV nA ns nV pA pF pp ppm ps sps V
Unit of Measure microwatts milli-ampere milli-second milli-volts nanoampere nanosecond nanovolts ohm picoampere picofarad peak-to-peak parts per million picosecond samples per second sigma: one standard deviation volts
dB fF Hz KB Kbit kHz k MHz M A F H s V Vrms
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Absolute Maximum Ratings
Table 8. Absolute Maximum Ratings
Symbol TSTG Storage Temperature Description Min -55 25 Typ Max +100
o
Units C
Notes Higher storage temperatures will reduce data retention time. Recommended storage temperature is +25oC 25oC. Extended duration storage temperatures above 65oC will degrade reliability.
TA Vdd VIO VIOZ IMIO IMAIO ESD LU
Ambient Temperature with Power Applied Supply Voltage on Vdd Relative to Vss DC Input Voltage DC Voltage Applied to Tri-state Maximum Current into any Port Pin Maximum Current into any Port Pin Configured as Analog Driver Electro Static Discharge Voltage Latch-up Current
-40 -0.5 Vss - 0.5 Vss - 0.5 -25 -50 2000 -
- - - - - - - -
+85 +6.0
o
C
V
Vdd + 0.5 V Vdd + 0.5 V +50 +50 - 200 mA mA V mA Human Body Model ESD.
Operating Temperature
Table 9. Operating Temperature
Symbol TA TJ Ambient Temperature Junction Temperature Description Min -40 -40 - - Typ Max +85 +100
o
Units C
Notes The temperature rise from ambient to junction is package specific. See "Thermal Impedances per Package" on page 36. The user must limit the power consumption to comply with this requirement.
oC
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CY8CLED16
DC Electrical Characteristics
DC Chip-Level Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 10. DC Chip-Level Specifications
Symbol Vdd IDD Supply Voltage Supply Current Description Min 3.00 - - 8 Typ Max 5.25 14 V mA Units Notes See DC POR and LVD specifications, Table 3-15 on page 27. Conditions are 5.0V, TA = 25 oC, CPU = 3 MHz, SYSCLK doubler disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 0.366 kHz. Conditions are Vdd = 3.3V, TA = 25 oC, CPU = 3 MHz, SYSCLK doubler disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 0.366 kHz. Conditions are Vdd = 3.3V, TA = 25 oC, CPU = 0.75 MHz, SYSCLK doubler disabled, VC1 = 0.375 MHz, VC2 = 23.44 kHz, VC3 = 0.09 kHz. Conditions are with internal slow speed oscillator, Vdd = 3.3V, -40 oC TA 55 oC. Conditions are with internal slow speed oscillator, Vdd = 3.3V, 55 oC < TA 85 oC. Conditions are with properly loaded, 1 W max, 32.768 kHz crystal. Vdd = 3.3V, -40 oC TA 55 oC. ISBXTLH Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and 32 kHz crystal oscillator active. - 5 27 A Conditions are with properly loaded, 1 W max, 32.768 kHz crystal. Vdd = 3.3V, 55 oC < TA 85
o
IDD3
Supply Current
-
5
9
mA
IDDP
Supply current when IMO = 6 MHz using SLIMO mode.
-
2
3
mA
ISB ISBH ISBXTL
Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and internal slow oscillator active. Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and internal slow oscillator active. Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, internal slow oscillator, and 32 kHz crystal oscillator active.
- - -
3 4 4
10 25 12
A A A
C.
VREF
Reference Voltage (Bandgap)
1.28
1.3
1.32
V
Trimmed for appropriate Vdd.
DC General Purpose IO Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 11. DC GPIO Specifications
Symbol RPU RPD VOH Pull up Resistor Pull down Resistor High Output Level Description 4 4 Vdd - 1.0 Min Typ 5.6 5.6 - 8 8 - Max Units k k V IOH = 10 mA, Vdd = 4.75 to 5.25V (8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). 80 mA maximum combined IOH budget. IOL = 25 mA, Vdd = 4.75 to 5.25V (8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). 150 mA maximum combined IOL budget. Vdd = 3.0 to 5.25. Vdd = 3.0 to 5.25. Gross tested to 1 A. Package and pin dependent. Temp = 25oC. Package and pin dependent. Temp = 25oC. Notes
VOL
Low Output Level
-
-
0.75
V
VIL VIH VH IIL CIN COUT
Input Low Level Input High Level Input Hysterisis Input Leakage (Absolute Value) Capacitive Load on Pins as Input Capacitive Load on Pins as Output
- 2.1 - - - -
- - 60 1 3.5 3.5
0.8
V V
- - 10 10
mV nA pF pF
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CY8CLED16
DC Operational Amplifier Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Capacitor PSoC blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block. Typical parameters apply to 5V at 25C and are for design guidance only. Table 12. 5V DC Operational Amplifier Specifications
Symbol VOSOA Description Input Offset Voltage (absolute value) Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High TCVOSOA IEBOA CINOA VCMOA Average Input Offset Voltage Drift Input Leakage Current (Port 0 Analog Pins) Input Capacitance (Port 0 Analog Pins) Common Mode Voltage Range. All Cases, except highest. Power = High, Opamp Bias = High CMRROA GOLOA VOHIGHOA VOLOWOA ISOA Common Mode Rejection Ratio Open Loop Gain High Output Voltage Swing (internal signals) Low Output Voltage Swing (internal signals) Supply Current (including associated AGND buffer) Power = Low, Opamp Bias = Low Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = Low Power = High, Opamp Bias = High PSRROA Supply Voltage Rejection Ratio - - - - - - 67 150 300 600 1200 2400 4600 80 200 400 800 1600 3200 6400 - A A A A A A dB Vss VIN (Vdd - 2.25) or (Vdd - 1.25V) VIN Vdd. 60 80 Vdd - .01 - - - - - - - - 0.1 dB dB V V - - - - - - 0.0 0.5 1.6 1.3 1.2 7.0 200 4.5 - - 10 8 7.5 35.0 - 9.5 Vdd Vdd - 0.5 mV mV mV V/oC pA pF V V Gross tested to 1 A. Package and pin dependent. Temp = 25 oC. Min Typ Max Units Notes
Table 13. 3.3V DC Operational Amplifier Specifications
Symbol VOSOA Description Input Offset Voltage (absolute value) Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = High High Power is 5 Volts Only TCVOSOA IEBOA CINOA VCMOA CMRROA GOLOA VOHIGHOA VOLOWOA Average Input Offset Voltage Drift Input Leakage Current (Port 0 Analog Pins) Input Capacitance (Port 0 Analog Pins) Common Mode Voltage Range Common Mode Rejection Ratio Open Loop Gain High Output Voltage Swing (internal signals) Low Output Voltage Swing (internal signals) - - - 0 60 80 Vdd - .01 - 7.0 200 4.5 - - - - - 35.0 - 9.5 Vdd - - - .01 V/oC pA pF V dB dB V V Gross tested to 1 A. Package and pin dependent. Temp = 25 oC. - - 1.65 1.32 10 8 mV mV Min Typ Max Units Notes
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Table 13. 3.3V DC Operational Amplifier Specifications (continued)
ISOA Supply Current (including associated AGND buffer) Power = Low, Opamp Bias = Low Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = Low Power = High, Opamp Bias = High PSRROA Supply Voltage Rejection Ratio - - - - - - 54 150 300 600 1200 2400 - 80 200 400 800 1600 3200 - - dB A A A A A Not Allowed Vss VIN (Vdd - 2.25) or (Vdd - 1.25V) VIN Vdd
DC Low Power Comparator Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V at 25C and are for design guidance only. Table 14. DC Low Power Comparator Specifications
Symbol VREFLPC ISLPC VOSLPC LPC supply current LPC voltage offset Description Low power comparator (LPC) reference voltage range - - Min 0.2 - 10 2.5 Typ 40 30 Max Vdd - 1 V A mV Units Notes
DC Analog Output Buffer Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 15. 5V DC Analog Output Buffer Specifications
Symbol VOSOB TCVOSOB VCMOB ROUTOB Description Input Offset Voltage (Absolute Value) Average Input Offset Voltage Drift Common-Mode Input Voltage Range Output Resistance Power = Low Power = High VOHIGHOB High Output Voltage Swing (Load = 32 ohms to Vdd/2) Power = Low Power = High - - 0.5 x Vdd + 1.3 0.5 x Vdd + 1.3 VOLOWOB Low Output Voltage Swing (Load = 32 ohms to Vdd/2) Power = Low Power = High - - - - 0.5 x Vdd - 1.3 0.5 x Vdd - 1.3 ISOB Supply Current Including Bias Cell (No Load) Power = Low Power = High PSRROB Supply Voltage Rejection Ratio - - 40 1.1 2.6 64 2 5 - mA mA dB V V - - - - 1 1 - - V V - - 0.5 Min 3 +6 - Typ 12 - Vdd - 1.0 Max Units mV V/C V Notes
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Table 16. 3.3V DC Analog Output Buffer Specifications
Symbol VOSOB TCVOSOB VCMOB ROUTOB Description Input Offset Voltage (Absolute Value) Average Input Offset Voltage Drift Common-Mode Input Voltage Range Output Resistance Power = Low Power = High VOHIGHOB High Output Voltage Swing (Load = 1k ohms to Vdd/2) Power = Low Power = High 0.5 x Vdd + 1.0 0.5 x Vdd + 1.0 VOLOWOB Low Output Voltage Swing (Load = 1k ohms to Vdd/2) Power = Low Power = High - - - - 0.5 x Vdd - 1.0 0.5 x Vdd - 1.0 ISOB Supply Current Including Bias Cell (No Load) Power = Low Power = High PSRROB Supply Voltage Rejection Ratio - 60 0.8 2.0 64 1 5 - mA mA dB V V - - - - V V - - - - 10 10 - - 0.5 Min 3 +6 Typ 12 - Vdd - 1.0 Max Units mV V/C V Notes
DC Switch Mode Pump Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 17. DC Switch Mode Pump (SMP) Specifications
Symbol VPUMP 5V VPUMP 3V IPUMP Description 5V Output Voltage at Vdd from Pump 3V Output Voltage at Vdd from Pump Available Output Current VBAT = 1.5V, VPUMP = 3.25V VBAT = 1.8V, VPUMP = 5.0V VBAT5V VBAT3V VBATSTART Input Voltage Range from Battery Input Voltage Range from Battery Minimum Input Voltage from Battery to Start Pump 8 5 1.8 1.0 1.2 - - - - - - - 5.0 3.3 - mA mA V V V Min 4.75 3.00 Typ 5.0 3.25 Max 5.25 3.60 V V Units Notes Configuration of footnote.a Average, neglecting ripple. SMP trip voltage is set to 5.0V. Configuration of footnote.a Average, neglecting ripple. SMP trip voltage is set to 3.25V. Configuration of footnote.a SMP trip voltage is set to 3.25V. SMP trip voltage is set to 5.0V. Configuration of footnote.a SMP trip voltage is set to 5.0V. Configuration of footnote.a SMP trip voltage is set to 3.25V. Configuration of footnote.a 0oC TA 100. 1.25V at TA = -40oC. VPUMP_Line Line Regulation (over VBAT range) - 5 - %VO Configuration of footnote.a VO is the "Vdd Value for PUMP Trip" specified by the VM[2:0] setting in the DC POR and LVD Specification, Table 3-15 on page 27. Configuration of footnote.a VO is the "Vdd Value for PUMP Trip" specified by the VM[2:0] setting in the DC POR and LVD Specification, Table 3-15 on page 27. Configuration of footnote.a Load is 5 mA. Configuration of footnote.a Load is 5 mA. SMP trip voltage is set to 3.25V.
VPUMP_Loa
d
Load Regulation
-
5
-
%VO
VPUMP_Rip
ple
Output Voltage Ripple (depends on capacitor/load) Efficiency
- 35
100 50
- -
mVpp %
E3
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Table 17. DC Switch Mode Pump (SMP) Specifications (continued)
FPUMP DCPUMP Switching Frequency Switching Duty Cycle - - 1.4 50 - - MHz %
a. L1 = 2 H inductor, C1 = 10 F capacitor, D1 = Schottky diode. See Figure 5.
Figure 5. Basic Switch Mode Pump Circuit
D1
DC Analog Reference Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block. Reference control power is high.
Vdd
V PUMP
L1 V BAT
C1 SMP
+
Battery
PSoC
Vss
Table 18. 5V DC Analog Reference Specifications
Symbol VBG5 - - - - - - - - - - - AGND = Vdd/2a AGND = 2 x BandGapa AGND = P2[4] (P2[4] = AGND = BandGapa AGND = 1.6 x BandGapa AGND Block to Block Variation (AGND = Vdd/2) RefHi = Vdd/2 + BandGap RefHi = 3 x BandGap RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V) RefHi = P2[4] + BandGap (P2[4] = Vdd/2) RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V)
a
Description Bandgap Voltage Reference 5V
Min 1.28 Vdd/2 0.02 2.52
Typ 1.30 Vdd/2 2.60 P2[4] 1.3 2.08 0.000
Max 1.32 Vdd/2 + 0.02 2.72 P2[4] + 0.013 1.34 2.13 0.034 V V V V V V V V V V V V
Units
Vdd/2)a
P2[4] 0.013 1.27 2.03 -0.034
Vdd/2 +
1.21 3.75 P2[6] + 2.478 P2[4] + 1.218 P2[4] + P2[6] 0.058 2.50 4.02
Vdd/2 +
1.3 3.9 P2[6] + 2.6 P2[4] + 1.3 P2[4] + P2[6] 2.60 4.16
Vdd/2 +
1.382 4.05 P2[6] + 2.722 P2[4] + 1.382 P2[4] + P2[6] + 0.058 2.70 4.29
- - - - - - -
RefHi = 2 x BandGap RefHi = 3.2 x BandGap RefLo = Vdd/2 - BandGap RefLo = BandGap RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V) RefLo = P2[4] - BandGap (P2[4] = Vdd/2) RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V)
V V V V V V V
Vdd/2 1.369 1.20 2.489 P2[6] P2[4] 1.368 P2[4] P2[6] 0.042
Vdd/2 1.30 1.30 2.6 P2[6] P2[4] 1.30 P2[4] P2[6]
Vdd/2 1.231 1.40 2.711 P2[6] P2[4] 1.232 P2[4] P2[6] + 0.042
a. AGND tolerance includes the offsets of the local buffer in the PSoC block. Bandgap voltage is 1.3V 0.02V.
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Table 19. 3.3V DC Analog Reference Specifications
Symbol VBG33 - - - - - - - - - - - AGND = Vdd/2a AGND = 2 x BandGapa AGND = P2[4] (P2[4] = Vdd/2) AGND = BandGapa AGND = 1.6 x BandGap
a a
Description Bandgap Voltage Reference 3.3V
Min 1.28 Vdd/2 0.02 P2[4] 0.009 1.27 2.03 -0.034
Typ 1.30 Vdd/2
Max 1.32 Vdd/2 + 0.02 P2[4] + 0.009 1.34 2.13 0.034 V V
Units
Not Allowed P2[4] 1.30 2.08 0.000 V V V mV
AGND Block to Block Variation (AGND = Vdd/2) RefHi = Vdd/2 + BandGap RefHi = 3 x BandGap RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V) RefHi = P2[4] + BandGap (P2[4] = Vdd/2)
Not Allowed Not Allowed Not Allowed Not Allowed P2[4] + P2[6] 0.042 2.50 P2[4] + P2[6] 2.60 P2[4] + P2[6] + 0.042 2.70 V
RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V)
- - - - - - -
RefHi = 2 x BandGap RefHi = 3.2 x BandGap RefLo = Vdd/2 - BandGap RefLo = BandGap RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V) RefLo = P2[4] - BandGap (P2[4] = Vdd/2) RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V)
V
Not Allowed Not Allowed Not Allowed Not Allowed Not Allowed P2[4] P2[6] 0.036 P2[4] P2[6] P2[4] P2[6] + 0.036 V
a. AGND tolerance includes the offsets of the local buffer in the PSoC block. Bandgap voltage is 1.3V 0.02V.
DC Analog PSoC Block Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 20. DC Analog PSoC Block Specifications
Symbol RCT CSC Description Resistor Unit Value (Continuous Time) Capacitor Unit Value (Switch Cap) - - Min 80 Typ 12.2 - - Max fF Units k Notes
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DC POR, SMP, and LVD Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 21. DC POR, SMP, and LVD Specifications
Symbol VPPOR0R VPPOR1R VPPOR2R VPPOR0 VPPOR1 VPPOR2 VPH0 VPH1 VPH2 VLVD0 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b Vdd Value for PPOR Trip (negative ramp) PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b PPOR Hysteresis PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b Vdd Value for LVD Trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b Vdd Value for SMP Trip VPUMP0 VPUMP1 VPUMP2 VPUMP3 VPUMP4 VPUMP5 VPUMP6 VPUMP7 VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b 2.96 3.03 3.18 4.11 4.55 4.63 4.72 4.90 3.02 3.10 3.25 4.19 4.64 4.73 4.82 5.00 3.08 3.16 3.32 4.28 4.74 4.82 4.91 5.10 V V V V V V V V V 2.86 2.96 3.07 3.92 4.39 4.55 4.63 4.72 2.92 3.02 3.13 4.00 4.48 4.64 4.73 4.81 2.98a 3.08 3.20 4.08 4.57 4.74b 4.82 4.91 V V V V V V V V V - - - 92 0 0 - - - mV mV mV - 2.82 4.39 4.55 - V V V - Description Vdd Value for PPOR Trip (positive ramp) 2.91 4.39 4.55 - V V V Min Typ Max Units Notes
a. Always greater than 50 mV above PPOR (PORLEV = 00) for falling supply. b. Always greater than 50 mV above PPOR (PORLEV = 10) for falling supply.
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DC Programming Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 22. DC Programming Specifications
Symbol IDDP VILP VIHP IILP IIHP VOLV VOHV FlashENPB FlashENT FlashDR Description Supply Current During Programming or Verify Input Low Voltage During Programming or Verify Input High Voltage During Programming or Verify Input Current when Applying Vilp to P1[0] or P1[1] During Programming or Verify Input Current when Applying Vihp to P1[0] or P1[1] During Programming or Verify Output Low Voltage During Programming or Verify Output High Voltage During Programming or Verify Flash Endurance (per block) Flash Endurance (total)a Flash Data Retention - - 2.2 - - - Vdd - 1.0 50,000 1,800,00 0 10 Min 10 - - - - - - - - - Typ Max 30 0.8 - 0.2 1.5 Vss + 0.75 Vdd - - - V V mA mA V V - - Years Erase/write cycles per block. Erase/write cycles. Driving internal pull-down resistor. Driving internal pull-down resistor. Units mA Notes
a. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees more than 50,000 cycles). For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.
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AC Electrical Characteristics
AC Chip-Level Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Note See the individual user module data sheets for information on maximum frequencies for user modules. Table 23. AC Chip-Level Specifications
Symbol FIMO24 Description Internal Main Oscillator Frequency for 24 MHz Min 23.4 24 Typ Max 24.6a,b,c Units MHz Notes Trimmed for 5V or 3.3V operation using factory trim values. See the figure on page 19. SLIMO Mode = 0. Trimmed for 5V or 3.3V operation using factory trim values. See the figure on page 19. SLIMO Mode = 1.
FIMO6
Internal Main Oscillator Frequency for 6 MHz
5.75
6
6.35a,b,c
MHz
FCPU1 FCPU2 F48M F24M F32K1 F32K2 FPLL Jitter24M2 TPLLSLEW TPLLSLEWLOW TOS TOSACC
CPU Frequency (5V Nominal) CPU Frequency (3.3V Nominal) Digital PSoC Block Frequency Digital PSoC Block Frequency Internal Low Speed Oscillator Frequency External Crystal Oscillator PLL Frequency 24 MHz Period Jitter (PLL) PLL Lock Time PLL Lock Time for Low Gain Setting External Crystal Oscillator Startup to 1% External Crystal Oscillator Startup to 100 ppm
0.93 0.93 0 0 15 - - - 0.5 0.5 - -
24 12 48 24 32 32.768 23.986 - - - 250 300
24.6a,b 12.3b,c 49.2
a,b,d
MHz MHz MHz MHz kHz kHz MHz ps ms ms ms ms The crystal oscillator frequency is within 100 ppm of its final value by the end of the Tosacc period. Correct operation assumes a properly loaded 1 uW maximum drive level 32.768 kHz crystal. 3.0V Vdd 5.5V, -40 oC TA 85 oC. Refer to the AC Digital Block Specifications below.
24.6b, d 64 - - 600 10 50 500 600
Accuracy is capacitor and crystal dependent. 50% duty cycle. A multiple (x732) of crystal frequency.
Jitter32k TXRST DC24M Step24M Fout48M Jitter24M1 FMAX TRAMP
32 kHz Period Jitter External Reset Pulse Width 24 MHz Duty Cycle 24 MHz Trim Step Size 48 MHz Output Frequency 24 MHz Period Jitter (IMO)
- 10 40 - 46.8 -
100 - 50 50 48.0 600 - - 12.3 - - 60 - 49.2a,c
ns s % kHz MHz ps MHz s Trimmed. Utilizing factory trim values.
Maximum frequency of signal on row input or row out- - put. Supply Ramp Time 0
a. b. c. d.
4.75V < Vdd < 5.25V. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range. 3.0V < Vdd < 3.6V. See Application Note AN2012 "Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation" for information on trimming for operation at 3.3V. See the individual user module data sheets for information on maximum frequencies for user modules.
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Figure 6. PLL Lock Timing Diagram
PLL Enable
TPLLSLEW 24 MHz
FPLL
PLL Gain
0
Figure 7. PLL Lock for Low Gain Setting Timing Diagram
PLL Enable
TPLLSLEWLOW 24 MHz
FPLL
PLL Gain
1
Figure 8. External Crystal Oscillator Startup Timing Diagram
32K Select
TOS 32 kHz
F32K2
Figure 9. 24 MHz Period Jitter (IMO) Timing Diagram
Jitter24M1
F 24M
Figure 10. 32 kHz Period Jitter (ECO) Timing Diagram
Jitter32k
F 32K2
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AC General Purpose IO Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 24. AC GPIO Specifications
Symbol FGPIO TRiseF TFallF TRiseS TFallS Description GPIO Operating Frequency Rise Time, Normal Strong Mode, Cload = 50 pF Fall Time, Normal Strong Mode, Cload = 50 pF Rise Time, Slow Strong Mode, Cload = 50 pF Fall Time, Slow Strong Mode, Cload = 50 pF 0 3 2 10 10 Min - - - 27 22 Typ 18 18 - - Max 12.3 Units MHz ns ns ns ns Notes Normal Strong Mode Vdd = 4.75 to 5.25V, 10% - 90% Vdd = 4.75 to 5.25V, 10% - 90% Vdd = 3 to 5.25V, 10% - 90% Vdd = 3 to 5.25V, 10% - 90%
Figure 11. GPIO Timing Diagram
90% GPIO Pin Output Voltage 10%
AC Operational Amplifier Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block. Power = High and Opamp Bias = High is not supported at 3.3V.
TRiseF TRiseS
TFallF TFallS
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Table 25. 5V AC Operational Amplifier Specifications
Symbol TROA Description Rising Settling Time to 0.1% for a 1V Step (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High TSOA Falling Settling Time to 0.1% for a 1V Step (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High SRROA Rising Slew Rate (20% to 80%) of a 1V Step (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High SRFOA Falling Slew Rate (20% to 80%) of a 1V Step (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High BWOA Gain Bandwidth Product Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High ENOA Noise at 1 kHz (Power = Medium, Opamp Bias = High) 0.75 3.1 5.4 - - - - 100 - - - - MHz MHz MHz nV/rt-Hz 0.01 0.5 4.0 - - - - - - V/s V/s V/s 0.15 1.7 6.5 - - - - - - V/s V/s V/s - - - - - - 5.9 0.92 0.72 s s s - - - - - - 3.9 0.72 0.62 s s s Min Typ Max Units Notes
Table 26. 3.3V AC Operational Amplifier Specifications
Symbol TROA Description Rising Settling Time to 0.1% of a 1V Step (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High TSOA Falling Settling Time to 0.1% of a 1V Step (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High SRROA Rising Slew Rate (20% to 80%) of a 1V Step (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High SRFOA Falling Slew Rate (20% to 80%) of a 1V Step (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High BWOA Gain Bandwidth Product Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High ENOA Noise at 1 kHz (Power = Medium, Opamp Bias = High) 0.67 2.8 - - - 100 - - - MHz MHz nV/rt-Hz 0.24 1.8 - - - - V/s V/s 0.31 2.7 - - - - V/s V/s - - - - 5.41 0.72 s s - - - - 3.92 0.72 s s Min Typ Max Units Notes
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When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1k resistance and the external capacitor. Figure 12. Typical AGND Noise with P2[4] Bypass
dBV/rtHz 10000
0 0.01 0.1 1.0 10
1000
100 0.001
0.01
0.1 Freq (kHz)
1
10
100
At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high frequencies, increased power level reduces the noise spectrum level. Figure 13. Typical Opamp Noise
nV/rtHz 10000 PH_BH PH_BL PM_BL PL_BL 1000
100
10 0.001
0.01
0.1
Freq (kHz)
1
10
100
AC Low Power Comparator Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V at 25C and are for design guidance only. Table 27. AC Low Power Comparator Specifications
Symbol TRLPC LPC response time Description - Min - Typ 50 Max Units s Notes 50 mV overdrive comparator reference set within VREFLPC.
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AC Digital Block Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 28. AC Digital Block Specifications
Function All Functions Timer Description Maximum Block Clocking Frequency (> 4.75V) Maximum Block Clocking Frequency (< 4.75V) Capture Pulse Width Maximum Frequency, No Capture Maximum Frequency, With Capture Counter Enable Pulse Width Maximum Frequency, No Enable Input Maximum Frequency, Enable Input Dead Band Kill Pulse Width: Asynchronous Restart Mode Synchronous Restart Mode Disable Mode Maximum Frequency CRCPRS Maximum Input Clock Frequency (PRS Mode) CRCPRS Maximum Input Clock Frequency (CRC Mode) SPIM SPIS Maximum Input Clock Frequency Maximum Input Clock Frequency Width of SS_ Negated Between Transmissions Transmitter Maximum Input Clock Frequency Vdd 4.75V, 2 Stop Bits 20 50a 50 - - - - - 50a - - Receiver Maximum Input Clock Frequency Vdd 4.75V, 2 Stop Bits - -
a
Min
Typ
Max 49.2 24.6
Units MHz MHz ns MHz MHz ns MHz MHz
Notes 4.75V < Vdd < 5.25V. 3.0V < Vdd < 4.75V.
50a - - 50a - -
- - - - - -
- 49.2 24.6 - 49.2 24.6
4.75V < Vdd < 5.25V.
4.75V < Vdd < 5.25V.
- - - - - - - - - - - - -
- - - 49.2 49.2 24.6 8.2 4.1 - 24.6 49.2 24.6 49.2
ns ns ns MHz MHz MHz MHz ns ns MHz MHz MHz MHz Maximum data rate at 3.08 MHz due to 8 x over clocking. Maximum data rate at 6.15 MHz due to 8 x over clocking. Maximum data rate at 3.08 MHz due to 8 x over clocking. Maximum data rate at 6.15 MHz due to 8 x over clocking. Maximum data rate at 4.1 MHz due to 2 x over clocking. 4.75V < Vdd < 5.25V. 4.75V < Vdd < 5.25V.
a. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
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AC Analog Output Buffer Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 29. 5V AC Analog Output Buffer Specifications
Symbol TROB Power = Low Power = High TSOB Falling Settling Time to 0.1%, 1V Step, 100pF Load Power = Low Power = High SRROB Rising Slew Rate (20% to 80%), 1V Step, 100pF Load Power = Low Power = High SRFOB Falling Slew Rate (80% to 20%), 1V Step, 100pF Load Power = Low Power = High BWOB Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load Power = Low Power = High BWOB Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load Power = Low Power = High 300 300 - - - - kHz kHz 0.8 0.8 - - - - MHz MHz 0.55 0.55 - - - - V/s V/s 0.5 0.5 - - - - V/s V/s - - - - 3.4 3.4 s s Description Rising Settling Time to 0.1%, 1V Step, 100pF Load - - - - 4 4 s s Min Typ Max Units Notes
Table 30. 3.3V AC Analog Output Buffer Specifications
Symbol TROB Power = Low Power = High TSOB Falling Settling Time to 0.1%, 1V Step, 100pF Load Power = Low Power = High SRROB Rising Slew Rate (20% to 80%), 1V Step, 100pF Load Power = Low Power = High SRFOB Falling Slew Rate (80% to 20%), 1V Step, 100pF Load Power = Low Power = High BWOB Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load Power = Low Power = High BWOB Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load Power = Low Power = High 200 200 - - - - kHz kHz 0.7 0.7 - - - - MHz MHz .4 .4 - - - - V/s V/s .36 .36 - - - - V/s V/s - - - - 4 4 s s Description Rising Settling Time to 0.1%, 1V Step, 100pF Load - - - - 4.7 4.7 s s Min Typ Max Units Notes
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AC External Clock Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 31. 5V AC External Clock Specifications
Symbol FOSCEXT - - - Frequency High Period Low Period Power Up IMO to Switch Description Min 0.093 20.6 20.6 150 - - - - Typ Max 24.6 5300 - - Units MHz ns ns s Notes
Table 32. 3.3V AC External Clock Specifications
Symbol FOSCEXT Description Frequency with CPU Clock divide by 1 Min 0.093 - Typ Max 12.3 Units MHz Notes Maximum CPU frequency is 12 MHz at 3.3V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider will ensure that the fifty percent duty cycle requirement is met.
FOSCEXT
Frequency with CPU Clock divide by 2 or greater
0.186
-
24.6
MHz
- - -
High Period with CPU Clock divide by 1 Low Period with CPU Clock divide by 1 Power Up IMO to Switch
41.7 41.7 150
- - -
5300 - -
ns ns s
AC Programming Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 33. AC Programming Specifications
Symbol TRSCLK TFSCLK TSSCLK THSCLK FSCLK TERASEB TWRITE TDSCLK TDSCLK3 Rise Time of SCLK Fall Time of SCLK Data Set up Time to Falling Edge of SCLK Data Hold Time from Falling Edge of SCLK Frequency of SCLK Flash Erase Time (Block) Flash Block Write Time Data Out Delay from Falling Edge of SCLK Data Out Delay from Falling Edge of SCLK Description 1 1 40 40 0 - - - - Min - - - - - 10 10 - - Typ 20 20 - - 8 - - 45 50 Max Units ns ns ns ns MHz ms ms ns ns Vdd > 3.6 3.0 Vdd 3.6 Notes
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AC I2C Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 34. AC Characteristics of the I2C SDA and SCL Pins
Standard Mode Symbol FSCLI2C THDSTAI2C TLOWI2C THIGHI2C TSUSTAI2C THDDATI2C TSUDATI2C TSUSTOI2C TBUFI2C TSPI2C SCL Clock Frequency Hold Time (repeated) START Condition. After this period, the first clock pulse is generated. LOW Period of the SCL Clock HIGH Period of the SCL Clock Set-up Time for a Repeated START Condition Data Hold Time Data Set-up Time Set-up Time for STOP Condition Bus Free Time Between a STOP and START Condition Pulse Width of spikes are suppressed by the input filter. Description 0 4.0 4.7 4.0 4.7 0 250 4.0 4.7 - Min - - - - - - - - - Max 100 0 0.6 1.3 0.6 0.6 0 100a 0.6 1.3 0 Fast Mode Min - - - - - - - - 50 Max 400 Units kHz s s s s s ns s s ns Notes
a. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
Figure 14. Definition for Timing for Fast/Standard Mode on the I2C Bus
SDA TLOWI2C TSUDATI2C THDSTAI2C
TSPI2C TBUFI2C
SCL S THDSTAI2C THDDATI2C THIGHI2C TSUSTAI2C TSUSTOI2C
Sr
P
S
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CY8CLED16
Packaging Information
This section illustrates the packaging specifications for the CY8CLED16 EZ-Color device, along with the thermal impedances for each package and the typical package capacitance on crystal pins. Important Note Emulation tools may require a larger area on the target PCB than the chip's footprint. For a detailed description of the emulation tools' dimensions, refer to the document titled PSoC Emulator Pod Dimensions at http://www.cypress.com/design/MR10161.
Packaging Dimensions
Figure 15. 28-Lead (210-Mil) SSOP
51-85079 *C
Figure 16. 48-Lead (300-Mil) SSOP
51-85061 *C 51 -85061-C
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CY8CLED16
Figure 17. 48-Lead (7x7 mm) QFN
001-12919 *A
Important Note For information on the preferred dimensions for mounting QFN packages, see the following Application Note at http://www.amkor.com/products/notes_papers/MLFAppNote.pdf. Important Note Pinned vias for thermal conduction are not required for the low-power PSoC device.
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CY8CLED16
Thermal Impedances
Table 35. Thermal Impedances per Package
Package 28 SSOP 48 SSOP 48 QFN** * TJ = TA + POWER x JA ** To achieve the thermal impedance specified for the QFN package, the center thermal pad should be soldered to the PCB ground plane. Typical
JA *
a schematic, BOM, and data sheet without writing a single line of code. Users work directly with application objects such as LEDs, switches, sensors, and fans. PSoC Express is available free of charge at http://www.cypress.com/psocexpress. PSoC DesignerTM At the core of the PSoC development software suite is PSoC Designer. Utilized by thousands of PSoC developers, this robust software has been facilitating PSoC designs for half a decade. PSoC Designer is available free of charge at http://www.cypress.com/psocdesigner. PSoC Programmer Flexible enough to be used on the bench in development, yet suitable for factory programming, PSoC Programmer works either as a standalone programming application or it can operate directly from PSoC Designer or PSoC Express. PSoC Programmer software is compatible with both PSoC ICE-Cube In-Circuit Emulator and PSoC MiniProg. PSoC programmer is available free of charge at http://www.cypress.com/psocprogrammer. CY3202-C iMAGEcraft C Compiler CY3202 is the optional upgrade to PSoC Designer that enables the iMAGEcraft C compiler. It can be purchased from the Cypress Online Store. At http://www.cypress.com, click the Online Store shopping cart icon at the bottom of the web page, and click PSoC (Programmable System-on-Chip) to view a current list of available items.
94 oC/W 69 oC/W 28
oC/W
Capacitance on Crystal Pins
Table 36. Typical Package Capacitance on Crystal Pins
Package 28 SSOP 48 SSOP 48 QFN Package Capacitance 2.8 pF 3.3 pF 1.8 pF
Solder Reflow Peak Temperature
Following is the minimum solder reflow peak temperature to achieve good solderability. Table 37. Solder Reflow Peak Temperature
Package 28 SSOP 48 SSOP 48 QFN Minimum Peak Temperature* 240oC 220oC 220oC Maximum Peak Temperature 260oC 260oC 260oC
Evaluation Tools
All evaluation tools can be purchased from the Cypress Online Store. CY3261A-RGB EZ-Color RGB Kit The CY3261A-RGB board is a preprogrammed HB LED color mix board with seven pre-set colors using the CY8CLED16 EZ-Color HB LED Controller. The board is accompanied by a CD containing the color selector software application, PSoC Express 3.0 Beta 2, PSoC Programmer, and a suite of documents, schematics, and firmware examples. The color selector software application can be installed on a host PC and is used to control the EZ-Color HB LED controller using the included USB cable. The application enables you to select colors via a CIE 1931 chart or by entering coordinates. The kit includes:

*Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 5oC with Sn-Pb or 245 5oC with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications.
Development Tool Selection
Software
This section presents the development tools available for all current PSoC device families including the CY8CLED16 EZ-Color family. PSoC ExpressTM As the newest addition to the PSoC development software suite, PSoC Express is the first visual embedded system design tool that allows a user to create an entire PSoC project and generate
Training Board (CY8CLED16) One mini-A to mini-B USB Cable PSoC Express CD-ROM Design Files and Application Installation CD-ROM
To program and tune this kit via PSoC Express 3.0 you must use a Mini Programmer Unit (CY3217 Kit) and a CY3240-I2CUSB kit.
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CY3210-MiniProg1 The CY3210-MiniProg1 kit allows a user to program PSoC devices via the MiniProg1 programming unit. The MiniProg is a small, compact prototyping programmer that connects to the PC via a provided USB 2.0 cable. The kit includes:

Getting Started Guide USB 2.0 Cable
CY3207ISSP In-System Serial Programmer (ISSP) The CY3207ISSP is a production programmer. It includes protection circuitry and an industrial case that is more robust than the MiniProg in a production-programming environment. Note: CY3207ISSP needs special software and is not compatible with PSoC Programmer. The kit includes:

MiniProg Programming Unit MiniEval Socket Programming and Evaluation Board 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample 28-Pin CY8C27443-24PXI PDIP PSoC Device Sample PSoC Designer Software CD Getting Started Guide USB 2.0 Cable
CY3207 Programmer Unit PSoC ISSP Software CD 110 ~ 240V Power Supply, Euro-Plug Adapter USB 2.0 Cable
CY3210-PSoCEval1 The CY3210-PSoCEval1 kit features an evaluation board and the MiniProg1 programming unit. The evaluation board includes an LCD module, potentiometer, LEDs, and plenty of breadboarding space to meet all of your evaluation needs. The kit includes:

Accessories (Emulation and Programming)
Table 38. Emulation and Programming Accessories
Part # Pin Package Flex-Pod Kita CY3250-29XXX CY3250-29XXX CY3250-29XXX QFN Foot Kitb CY3250-28 SSOP-FK CY3250-48 SSOP-FK CY3250-48 QFN-FK Adapterc
Evaluation Board with LCD Module MiniProg Programming Unit 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2) PSoC Designer Software CD Getting Started Guide USB 2.0 Cable
CY8CLED16- 28 SSOP 28PVXI CY8CLED16- 48 SSOP 48PVXI CY8CLED16- 48 QFN 48LFXI
Adapters can be found at http://www.emulation.com.
Device Programmers
All device programmers can be purchased from the Cypress Online Store. CY3216 Modular Programmer The CY3216 Modular Programmer kit features a modular programmer and the MiniProg1 programming unit. The modular programmer includes three programming module cards and supports multiple Cypress products. The kit includes:

a. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods. b. Foot kit includes surface mount feet that can be soldered to the target PCB. c. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters can be found at http://www.emulation.com.
3rd-Party Tools Several tools have been specially designed by the following 3rd-party vendors to accompany PSoC devices during development and production. Specific details for each of these tools can be found at http://www.cypress.com under DESIGN RESOURCES >> Evaluation Boards. Build a PSoC Emulator into Your Board For details on how to emulate your circuit before going to volume production using an on-chip debug (OCD) non-production PSoC device, see Application Note "Debugging - Build a PSoC Emulator into Your Board - AN2323" at http://www.cypress.com/an2323.
Modular Programmer Base 3 Programming Module Cards MiniProg Programming Unit PSoC Designer Software CD
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CY8CLED16
Ordering Information
Key Device Features
The following table lists the CY8CLED16 EZ-Color devices' key package features and ordering codes. Table 39. Device Key Features and Ordering Information
Analog PSoC Blocks Switch Mode Pump Temperature Range Digital PSoC Blocks XRES Pin Digital IO Pins Ordering Code Package Analog Outputs Flash (Bytes) RAM (Bytes) Analog Inputs
28 Pin (210 Mil) SSOP 28 Pin (210 Mil) SSOP (Tape and Reel) 48 Pin (300 Mil) SSOP 48 Pin (300 Mil) SSOP (Tape and Reel) 48 Pin QFN 48 Pin QFN (Tape and Reel)
CY8CLED16-28PVXI CY8CLED16-28PVXIT CY8CLED16-48PVXI CY8CLED16-48PVXIT CY8CLED16-48LFXI CY8CLED16-48LFXIT
32K 32K 32K 32K 32K 32K
2K 2K 2K 2K 2K 2K
Yes Yes Yes Yes Yes Yes
-40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C
16 16 16 16 16 16
12 12 12 12 12 12
24 24 44 44 44 44
12 12 12 12 12 12
4 4 4 4 4 4
Yes Yes Yes Yes Yes Yes
Ordering Code Definitions
CY 8 C LED xx - xx xxxx Package Type: Thermal Rating: PX = PDIP Pb-Free C = Commercial SX = SOIC Pb-Free I = Industrial PVX = SSOP Pb-Free E = Extended LFX/LKX = QFN Pb-Free AX = TQFP Pb-Free Pin Count Part Number LED Family Code Technology Code: C = CMOS Marketing Code: 8 = Cypress PSoC Company ID: CY = Cypress
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CY8CLED16
Document History
Table 40. CY8CLED16 Data Sheet Revision History
Document Title: Revision ** CY8CLED16 EZ-Color HB LED Controller ECN # 1148504 Issue Date See ECN Origin of Change SFVTMP3 New document (revision **). Description of Change Document Number: 001-13105
Distribution: External/Public
Posting: None
(c) Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. PSoC DesignerTM, Programmable System-on-ChipTM, and PSoC ExpressTM are trademarks and PSoC(R) is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-13105 Rev. **
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